package yycore

import chisel3._
import chisel3.util._
import top.Settings

// General Parameter for MyCore
case class MyCoreConfig() {
  val XLEN = 64
  val DataBits = XLEN
  val DataBytes = DataBits / 8
  val AddrBits = 32
  val IBufSize = 4
  val FPGA = if(Settings.get("FPGAPlatform")) true else false
}
